Post

Replies

Boosts

Views

Activity

Reply to Floating point exception trapping on M1
You can decode the nature of the FPU exception in the SIGILL handler by declaring the third argument of your sigaction handler as a struct ucontext*, and then decoding scp->uc_mcontext->__es.esr in your handler. This is the value of the ESR_ELx, Exception Syndrome Register (ELx) register. If its top 6 bits (EC) are 0b101100, then the signal was triggered by a trapping AArch64 FPU operation. If in that case bit 23 of that register (TFV) is also 1, then the register's lower 7 bits will match what the lower 7 bits of the fpsr register would have been in case trapping would have been disabled (i.e., the kind of FPU exception triggered by the instruction). See section D7.2.27 of the ARMv8 architecture manual for more information.
Oct ’22